Performance Evaluation of Cache Replacement Policies for Multi-Core Processor Architectures in Data-Intensive Computing Workloads

Abstract

The swift expansion of data-heavy applications has markedly heightened the performance requirements on contemporary multi-core processor designs. Applications like large-scale analytics, graph processing, machine learning, database management, scientific computing, and cloud services generate a significant amount of memory traffic and often work with data sets that surpass the capacity of on-chip caches. As a result, efficient cache management has become a crucial factor in determining overall system performance. Among the various cache management strategies, cache replacement policies are particularly vital as they determine which cache block should be removed to make room for new data in a full cache. Traditional policies such as First-In-First-Out (FIFO), Least Recently Used (LRU), and random replacement are still widely adopted due to their straightforward concepts and low implementation complexity. However, workloads that are data-intensive and run on multi-core systems often display characteristics like irregular memory access patterns, high cache contention, inter-core interference, data sharing, streaming accesses, and rapidly changing reuse behavior, which can diminish the effectiveness of conventional replacement strategies.

This study offers a thorough performance assessment of cache replacement policies for multi-core processor architectures under typical data-intensive workloads. The research contrasts traditional policies, including FIFO, LRU, Pseudo-LRU (PLRU), and Random replacement, with more adaptive and reuse-aware strategies such as Segmented LRU (SLRU), Re-Reference Interval Prediction (RRIP)-based replacement, and Dynamic RRIP (DRRIP). The proposed methodology utilizes a controlled multi-core simulation framework where processor cores, private cache levels, and a shared last-level cache are set up to execute workload categories with varying memory behaviors. Performance metrics include cache hit rate, miss rate, average memory access time, instructions per cycle, execution time, memory traffic, and inter-core fairness. Realistic experimental data are generated across different core counts and workload classes to illustrate how replacement decisions affect processor efficiency.

The results reveal that no single replacement policy is universally superior. LRU is effective for workloads with strong temporal locality but struggles when streaming or scan-intensive accesses fill the cache. FIFO and Random policies are simpler to implement but generally result in higher miss rates for locality-sensitive workloads. PLRU offers a practical approximation to LRU but may select suboptimal victims under complex access patterns. RRIP and DRRIP show better adaptability, especially for mixed and data-intensive workloads with both high-reuse and low-reuse cache blocks. The findings indicate that adaptive reuse-aware replacement can enhance average last-level cache hit rates by about 8–17% compared to baseline FIFO and Random policies and can decrease average memory access time and execution cycles in high-contention multi-core environments.

The study highlights a significant research gap in the joint evaluation of replacement policies across diverse workloads, increasing core counts, shared-cache contention, and performance fairness. It proposes a systematic evaluation framework that connects cache behavior with workload characteristics and multi-core interference. The research concludes that future cache systems should increasingly adopt adaptive, workload-aware, and hardware-efficient replacement mechanisms. Future research opportunities include machine-learning-guided replacement, phase-aware adaptation, quality-of-service-aware cache management, energy-sensitive replacement, chiplet-based cache hierarchies, and replacement mechanisms optimized for heterogeneous CPU, GPU, and AI accelerator architectures.