A Hardware-Software Co-Design Approach for Low-Latency Signal Processing in Wearable Health Monitoring Devices

Abstract

Wearable health monitoring devices have become a crucial element in contemporary digital healthcare, as they allow for ongoing, non-invasive, and tailored monitoring of physiological parameters outside traditional clinical settings. These devices, which can track electrocardiography (ECG), photoplethysmography (PPG), blood oxygen saturation (SpO₂), body temperature, respiratory activity, physical movement, and other biosignals, are instrumental in early disease detection, managing chronic conditions, assessing fitness, caring for the elderly, and monitoring patients remotely. The effectiveness of these systems largely hinges on their capacity to process continuously gathered signals with minimal delay, satisfactory accuracy, low energy use, and dependable performance under stringent computational and memory limitations. Conventional wearable architectures often treat hardware selection and software development as mostly separate processes. In such setups, developers might choose a microcontroller and sensors initially and then try to optimize firmware and signal-processing algorithms. This step-by-step method can lead to performance issues because low-latency physiological monitoring relies on the interplay among sensor sampling, analog-to-digital conversion, buffering, memory transfers, processor scheduling, digital filtering, feature extraction, communication, and power management. Even a computationally efficient algorithm can result in high end-to-end latency if memory access is inefficient, while a powerful processor might waste energy if software tasks are not well scheduled. Therefore, a combined hardware-software co-design approach is essential. This research introduces a hardware-software co-design framework aimed at low-latency signal processing in wearable health monitoring devices. The proposed framework combines sensor acquisition hardware, low-power embedded processing, direct memory access (DMA), double buffering, real-time task scheduling, adaptive digital filtering, optimized feature extraction, lightweight machine-learning inference, and event-driven wireless communication. The architecture employs a heterogeneous processing strategy, where time-sensitive and computationally predictable tasks are assigned to optimized embedded hardware pathways, while adaptive and decision-oriented tasks are handled in software. The study employs a prototype-oriented experimental methodology using representative ECG, PPG, accelerometer, and temperature signals. A comparative evaluation is conducted against a traditional sequential embedded-processing architecture. The experimental analysis utilizes representative workload configurations to assess acquisition-to-decision latency, processing time, CPU utilization, memory footprint, energy consumption, throughput, and detection performance. The proposed co-designed architecture significantly reduces mean end-to-end latency from about 43.8 ms in the baseline architecture to 18.6 ms in the proposed design under the primary multi-sensor workload. Average CPU utilization drops from 78.4% to 51.7%, while estimated energy per processing cycle decreases by roughly 34%. The findings show that overlapping data acquisition with processing, minimizing memory-copy operations, employing adaptive processing pipelines, and using task-aware hardware acceleration can enhance responsiveness without sacrificing signal quality. The study offers a structured design methodology for wearable health devices, where hardware and software decisions are optimized together rather than separately. It also provides realistic performance-analysis procedures and architectural guidelines for developers of low-latency embedded health monitoring platforms. Future research could expand the framework with dedicated AI accelerators, ultra-low-power edge inference, advanced multimodal fusion, personalized adaptive models, hardware security mechanisms, and large-scale clinical validation.